This invention relates to the provision of a clock/buffer network in a mask-programmable logic device. More particularly, the invention relates to such a device in which a portion of the clock/buffer network is fixed, and a portion of the clock/buffer network is mask-programmable.
Programmable logic devices are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing”—i.e., opening—fusible links. Alternatively, the configuration may have been stored in a programmable read-only memory. These devices generally provided the user with the ability to configure the devices for “sum-of-products” (or “P-TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up table-type logic operations. At some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as P-TERM logic).
In all of the foregoing programmable logic devices, both the logic functions of particular logic elements in the device, and the interconnect for routing of signals between the logic elements, were programmable. More recently, mask-programmable logic devices have been provided. With mask-programmable logic devices, instead of selling all users the same device, the manufacturer manufactures a partial device with a standardized arrangement of logic elements whose functions are not programmable by the user, and which lacks any routing or interconnect resources.
The user provides the manufacturer of the mask-programmable logic device with the specifications of a desired device, which may be the configuration file for programming a comparable conventional programmable logic device. The manufacturer uses that information to add metallization layers to the partial device described above. Those additional layers program the logic elements by making certain connections within those elements, and also add interconnect routing between the logic elements. Mask-programmable logic devices can also be provided with embedded random access memory blocks, as described above in connection with conventional programmable logic devices. In such mask-programmable logic devices, if the embedded memory is configured as read-only memory or P-TERM logic, that configuration also is accomplished using the additional metallization layers.
While conventional programmable logic devices allow a user to easily design a device to perform a desired function, a conventional programmable logic device invariably includes resources that may not be used for a particular design. Moreover, in order to accommodate general purpose routing and interconnect resources, and the switching resources that allow signals from any logic element to reach any desired routing and interconnect resource, conventional programmable logic devices grow ever larger as more functionality is built into them, increasing the size and power consumption of such devices. The routing of signals through the various switching elements as they travel from one routing and interconnect resource to another also slows down signals.
The advent of mask-programmable logic devices has allowed users to prove a design in a conventional programmable logic device, but to commit the production version to a mask-programmable logic device which, for the same functionality, can be significantly smaller and use significantly less power, because the only interconnect and routing resources are those actually needed for the particular design. In addition, there are no general purpose switching elements consuming space or power, or slowing down signals.
On the other hand, conventional programmable logic devices are optimized for the distribution of device-wide signals such as clocks. Networks of device-wide conductors are located and routed to predetermine insertion delay and minimize skew in such device-wide signals, which becomes more significant as devices grow larger and more complex, so that on average the distribution network for such device-wide signals is as efficient as it can be. In addition, the general routing and interconnect resources in conventional programmable logic devices include additional device-wide conductors for other high-fanout signals, such as presets, clears, enables and other signals that may be generated in the user-designed logic such as high-fanout logic outputs. These resources, which give the user a way to efficiently distribute device-wide signals, are also frequently provided with generous buffering resources, to prevent degradation of such signals as a result of capacitive or other loading of the device-wide conductors.
However, in mask-programmable logic devices as described above, there are no predetermined routing resources. Therefore, the task of optimizing each design falls to the manufacturer in migrating the user's programmable device design to a mask-programmable device. This task can be very time consuming, and can greatly slow down the process of migrating the design. Accordingly, it would be desirable to be able to provide a mask-programmable logic device which preserves the timing characteristics of the conventional programmable logic device to which it is comparable, for which the time required to design any required high-fanout signal routing can be minimized, and whose die-size and power requirements are reduced as compared to the comparable conventional programmable logic device.